| IP Facts Table | |
|---|---|
| Core Specifics | |
| Supported Device Family | AMD Versal™ adaptive SoC, AMD Virtex 7, AMD UltraScale™ , AMD Kintex™ UltraScale™ , AMD Virtex™ UltraScale+™ , AMD Kintex™ UltraScale+™ , AMD Zynq™ UltraScale+™ MPSoC, AMD Artix™ UltraScale+™ |
| Supported User Interfaces |
AXI4-Stream 32-bit Optional AXI4-Lite |
| Resources | Performance and Utilization Web Page |
| Provided with Core | |
| Design Files | Encrypted RTL |
| Example Design | Verilog |
| Test Bench | Verilog |
| Constraints File | XDC |
| Simulation Model | Verilog |
| Supported S/W Driver | Linux |
| Tested Design Flows | |
| Design Entry | Not Applicable |
| Simulation | For supported simulators, see the Vivado Design Suite User Guide: Release Notes, Installation, and Licensing (UG973). |
| Synthesis | Not Applicable |
| Support | |
| Release Notes and Known Issues | Master Answer Record: N/A |
| All Vivado IP Change Logs | Master Vivado IP Change Logs: 72775 |
| Support web page | |
|
|