The following table shows the miscellaneous status and control signals.
| Name | Direction | Clock Domain | Description |
|---|---|---|---|
| ctl_tx_test_pattern_enable | Input | tx_clk_out |
Test pattern generation enable for the TX core. A value of 1 enables test mode. Corresponds to MDIO register bit 3.42.3 as defined in clause 45. Takes second precedence. |
| ctl_tx_test_pattern_select | Input | tx_clk_out | Corresponds to MDIO register bit 3.42.1 as defined in Clause 45 |
| ctl_tx_data_pattern_select | Input | tx_clk_out | Corresponds to MDIO register bit 3.42.0 as defined in Clause 45 |
| ctl_tx_test_pattern_seed_a[57:0] | Input | tx_clk_out | Corresponds to MDIO registers 3.34 through to 3.37 as defined in Clause 45 |
| ctl_tx_test_pattern_seed_b[57:0] | Input | tx_clk_out | Corresponds to MDIO registers 3.38 through to 3.41 as defined in Clause 45 |
| ctl_rx_test_pattern_enable | Input | rx_clk_out |
Test pattern enable for the RX core. A value of 1 enables test mode. Corresponds to MDIO register bit 3.42.2 as defined in Clause 45. Takes second precedence. |
| ctl_rx_data_pattern_select | Input | rx_clk_out | Corresponds to MDIO register bit 3.42.0 as defined in Clause 45. |
| stat_rx_test_pattern_mismatch | Output | rx_clk_out | Test pattern mismatch increment. A non-zero value in any cycle indicates how
many mismatches occurred for the test pattern in the RX core. This output is only
active when ctl_rx_test_pattern is set to a 1. This output can be
used to generate MDIO register as defined in Clause 45. This output is pulsed for
one clock cycle. |
| ctl_local_loopback | Input | Async | Sets GT in near-end PMA loopback |
| ctl_rx_process_lfi | Input | rx_clk_out |
When this input is set to 1, the RX core expects and processes LF control codes coming in from the transceiver. When set to 0, the RX core ignores LF control codes coming in from the transceiver. |
| stat_rx_valid_ctrl_code | Output | rx_clk_out | Indicates that a PCS block with a valid control code was received. |