The timing of a normal frame transfer is
shown in the following figure. When the client wants to transmit a frame, it asserts tx_axis_tvalid and places the data and control in tx_axis_tdata and tx_axis_tkeep in
the same clock cycle. When this data is accepted by the core, indicated by tx_axis_tready being asserted, the client must provide the next
cycle of data. If tx_axis_tready is not asserted by the
core, the client must hold the current valid data value until it is. The end of the packet
is in dictated to the core by tx_axis_tlast asserted for one
cycle. The bits of tx_axis_tkeep are set appropriately to
indicate the number of valid bytes in the final data transfer. tx_axis_tuser is also asserted to indicate a bad packet.
After tx_axis_tlast is deasserted, any
data and control is deemed invalid until tx_axis_tvalid is next
asserted.
