Overview - 1.2 English

The following diagram shows the instantiation of various modules and their hierarchy for a single core configuration of usxgmii_0 example design when the GT (serial transceiver) is inside the IP core. (Serial Transceiver is always a part of the example design for AMD Versal™ adaptive SoC.)

Sync registers and pipeline registers are used for to synchronize the data between the core and the GT. Clocking helper blocks are used to generate the required clock frequency for the core.

AXI4-Stream is available for datapath interface and AXI4-Lite is available for control and statistics interface.

The usxgmii_0_pkt_gen_mon module is used to generate the data packets for sanity testing. The packet generation and checking is controlled by an FSM module.

The Example Design consists of these optional modules:

• usxgmii _0_trans_debug: This module is present in the example design when you enable the Additional GT Control and Status Ports check box from the GT Selection and Configuration tab in AMD Vivado™ IDE. This module brings out all the GT channel dynamic reconfiguration port (DRP) ports, and some control and status ports of the transceiver module out of the USXGMII core.
• Retiming registers: When you select the Enable Retiming Register option from the GT Selection and Configuration tab, it includes a single stage pipeline register between the core and the GT to ease timing, using the gt_txusrclk2 and gt_rxusrclk2 for TX and RX paths respectively. However, by default two-stage registering is done for the signals between the GT and the core.

The following diagram shows the instantiation of various modules and their hierarchy for the multiple core configuration of the usxgmii_0 example design.