Performance and Resource Utilization - 1.2 English

USXGMII Ethernet Subsystem Product Guide (PG251)
Document ID
PG251
Release Date
2023-12-12
Version
1.2 English

For transceiver latency, see UltraScale Architecture GTY Transceivers User Guide (UG578) and Versal Adaptive SoC GTY and GTYP Transceivers Architecture Manual (AM002) for information on the transceiver latency.

For full details about performance and resource utilization, visit the Performance and Utilization web page.

Note: The default configuration for USXGMII IP is with Auto-Negotiation enabled. So the utilization summary page shows with the Auto-Negotiation feature enabled. If Auto-Negotiation is bypassed in the example design, the total number of LUTs for default configuration is approximately 2400.

Latency

These measurements are for the core only; they do not include the latency through the transceiver. The latency through the transceiver can be obtained from the relevant user guide.

Transmit Path Latency

As measured from the input port tx_axis_tdata[31:0] of the transmitter side AXI4-Stream (until that data appears on tx_serdes_data0[31:0] on the transceiver interface), the latency through the core for AMD UltraScale™ devices is thirteen periods of the 312.5 MHz transmit clock.

Receive Path Latency

As measured from the input into the core on rx_serdes_data0[31:0] until the data appears on rx_axis_tdata[31:0] of the receiver side AXI4-Stream interface, the latency through the core in the receive direction is seventeen cycles of the 312.5 MHz receive clock.