The following figure shows the block diagram of the USXGMII IP, not including the GT transceiver.
The USXGMII IP Core uses two data signals in each direction to convey frame data and link rate information between a single or multi-port PHY and the Ethernet MAC(s). The data signals operate at 10.3125 Gb/s (USXGMII/XFI), using clock data recovery (CDR) technology to recover the clock at the MAC and PHY serial interfaces. Due to the high speed of operation, each of these signal pairs is realized as differential pairs thus optimizing signal integrity while minimizing system noise.
The USXGMII core leverages the 64B/66B PCS defined in IEEE 802.3 Clause 49. Data replication is used to encapsulate lower Ethernet rates (10M, 100M, 1G, etc) into BASE-R 66b words for translation into a USXGMII stream via the Clause 49 PCS.
The PCS is unchanged with additional functionality being added via the "ordered set" mechanism defined by the IEEE Group.
TX Data Path
The 32-bit AXI4-Stream interface supports user-defined out-of-band preamble values, allowing USXGMII messages to be passed on packet preamble bytes.
On TX, every 32-bit word is replicated
several times according to the rate selected by the auto-negotiation with the link partner,
or by direct programming of the ctl_usxgmii_rate[2:0]
port
without auto-negotiation, when ctl_umii_an_bypass
= 1 (see
Port Descriptions for encoding). Code word replication is
used to pad out the less than 10GE rates, and Start and Terminate words are modified
according to the USXGMII specification for seamless decoding.
RX Datapath
On RX, replicated 32-bit words are discarded before the remaining unique packet data is passed on. The received preamble bytes are extracted from received packets and passed out alongside packet start of packets (SOPs).
As with the TX data path, when ctl_umii_an_bypass
= 1, the USXGMII RX rate is determined by ctl_usxgmii_rate[2:0]
(see Port Descriptions for encoding).
USXGMII at Lower Speeds
The following figures illustrate the start and termination of a packet transfer at 5 Gb/s.
Each word of the preamble and payload is replicated 2/4/10/100/1000 times for 5G/2.5G/1G/100M/10M, respectively.
Auto-Negotiation
In the USXGMII IP Core, the auto-negotiation is based on clause 37 of IEEE 802.3. The operation conforms to the description provided by EDCS-1467841 NBASE-T Universal SXGMII: Copper PHY ERS.
The USXGMII core creates three new types of
ordered sets, besides the existing local fault and the remote fault. The UsxgmiiChannelInfo
carries the auto-negotiation information. The
control register ctl_umii_an_mr_adv_ability
maps to UsxgmiiChannelInfo
. The other two are UmiiLocalFault
and UmiiRemoteFault
. This
ordered set is used to transfer the 16-bit UsxgmiiChannelInfo
word(s) between the link partners. The bit meanings are laid
out in EDCS-1467841. Amidst this data is the desired rate that can be specified using bits
11:9 of ctl_umii_an_mr_adv_ability
.
During auto-negotiation, each link partner
continuously broadcasts the UsxgmiiChannelInfo
word(s) to
the respective link partners, and each link partner examines the received channel
information message and compares that message to what was being broadcast.
Then, following the clause 37 protocol, the auto-negotiation circuit will idle the lanes for the link-time-out value, and then the circuit will set the negotiated rate and enable mission-mode.
Currently, the core provides an
autoneg_bypass
, similar in behavior to that of clause 73. When this is
set, the autoneg
function is disabled, and the operation is preset to
mission mode at the data rate that is set by the ctl_usxgmii_rate
input.
Currently, the auto-negotiation resolves the rate to the lowest requested rate. However, there is an ambiguity in EDCS-1467841 that does not specify how rates are to be resolved.
Clause 37 Auto-Negotiation Operation
Signal names are:
-
ctl_umii_an_mr_an_enable
-
ctl_umii_an_mr_restart_an
-
ctl_umii_an_mr_main_reset
-
ctl_umii_an_bypass
The ctl_umii_an_mr_main_reset
is not the
circuit reset input. It is the mr_main_reset
as defined in clause 37.
When ctl_umii_an_mr_main_reset
is asserted,
the auto-negotiation (AN) will hold the state AN_ENABLE. In this state, if
ctl_umii_an_mr_an_enable
is set, the AN will configure the PCS for a 10G
rate, and it will continuously send a zero usx_config
word, but it will not
do anything else until ctl_umii_an_mr_main_reset
is cleared. If
ctl_umii_an_mr_an_enable
is not set, the AN will set the PCS to
continuously send IDLES. The rate will be whatever was previously set. If there were no
previous negotiations, the rate set will be 10G. The AN will hold in state AN_ENABLE until
the ctl_umii_an_mr_main_reset
signal is removed.
When ctl_umii_an_mr_main_reset
is removed,
then, if ctl_umii_an_mr_an_enable
is set, the AN will proceed to state
AN_RESTART
, and it will begin to negotiate the link, as per clause 37. If
ctl_umii_an_mr_an_enable
is not set, the AN will go to state
AN_DISABLE_LINK_OK. In this state, the PCS is configured in mission mode, (that is, ready
for traffic), at whatever rate was previously negotiated, and the AN circuit holds
there.
If the ctl_umii_an_bypass
signal is set, it
automatically clears the internal mr_an_enable
signal into the AN circuit,
regardless of the setting of the ctl_umii_an_mr_an_enable
input. It also
automatically sets the PCS rate to whatever the ctl_usxgmii_rate
input is
set to, and it sets the PCS to mission-mode. The ctl_umii_an_bypass
signal
will also override the above described behavior of the
ctl_umii_an_mr_main_reset
. That is, the PCS will be configured into
mission mode as described regardless of how ctl_umii_an_mr_main_reset
and
ctl_umii_an_mr_an_enable
are set.
If the ctl_umii_an_bypass
signal is not set,
and the ctl_umii_an_mr_main_reset
is also not set, and if the
ctl_umii_an_mr_an_enable
is set, and then if
ctl_umii_an_mr_restart_an
is asserted, the AN will enter state
AN_RESTART, where it will proceed to negotiate the link, as per clause 37. To signal another
restart, the ctl_umii_an_mr_restart_an
has to be cycled. That is, it has to
be cleared and then set again. The restart is triggered on the positive transition of the
ctl_umii_an_mr_restart_an
signal.
Standards
The USXGMII IP conforms to the EDCS 1467841-NBASE-T USXGMII: Copper PHY ERS specification, revision 1.4 (AMD recommends that you join the NBASE-T Alliance to gain access to the USXGMII specification. See http://www.nbaset.org/alliance/become-participant/).