Shared logic includes all the shareable modules that can be present as part of the core or in the Example Design.
By default GT common, reset logic and clocking modules are present inside the IP core. In case of the following conditions, these modules will be placed outside the core so that they can be shared with other designs.
- When you select the Include GT subcore in example design option in the GT Selection and Configuration tab.
- When you select the Include Shared Logic in Example Design option in the Shared Logic tab.
When the shared logic in the example design is selected, a
new usxgmii_*_core_support.v
module will be instantiated between the
usxgmii_*_exdes.v
and DUT (that is, usxgmii_*.v
). This
module will have all the sub modules that can be shared between multiple designs.
The following figure shows the implementation when shared logic is instantiated in the example design for single core.
The following image shows the implementation when shared logic is instantiated in the example design for multiple cores.
These modules are part of the shared logic wrapper:
-
*_clocking_wrapper
This module contains all the clocking resources that can be shared with other core instances.
-
*_common_wrapper
This module contains the GT common module that can be shared with other core instances.
-
*_reset_wrapper
This module contains the reset logic for the specified configuration.