Transceiver Interface - 1.2 English

USXGMII Ethernet Subsystem Product Guide (PG251)
Document ID
PG251
Release Date
2023-12-12
Version
1.2 English

The following table shows the transceiver I/O ports for the USXGMII subsystem. Refer to Clocking and Resets in Chapter 3 for details regarding each clock domain.

Table 1. Transceiver Interface
Name Direction

Clock Domain

 Description
gtwiz_reset_tx_datapath_* Input Async GT TX reset
gtwiz_reset_rx_datapath_* Input Async GT RX reset
gt_refclk_p Input   Differential reference clock input for the SerDes, positive phase.
gt_refclk_n Input   Differential reference clock input for the SerDes, negative phase.
gt_rxp_in_* Input   Serial data from the line; positive phase of the differential signal.
gt_rxn_in_* Input   Serial data from the line; negative phase of the differential signal.
gt_txp_out_* Output   Serial data to the line; positive phase of the differential signal.
gt_txn_out_* Output   Serial data to the line; negative phase of the differential signal.
dclk Input   Free running clock to GT
gt_loopback_in_* Input Async

GT loopback input signal.

Refer to the GT user guide.

This port is available when the Include GT subcore in core option is selected in the GT Selection and Configuration tab.
gt_loopback_out_* Output Async

GT loopback output signal from AXI4-Lite register map.

Refer to the GT user guide.

This port is available when Include AXI4-Lite is selected from the Configuration tab and the Include GT subcore in the example design option is selected in the GT Selection and Configuration tab.
rxgearboxslip_in_* Output RXUSRCLK2

Rxgearboxslip signal from core to GT.

This port is available when the Include GT subcore in the example design option is selected in the GT Selection and Configuration tab.
rxdatavalid_out_* Input RXUSRCLK2

RX data valid signal from GT to core.

This port is available when the Include GT subcore in the example design option is selected in the GT Selection and Configuration tab.
rx_serdes_data_out_* Input RXUSRCLK2

RX data signal from GT to core.

This port is available when the Include GT subcore in example design option is selected in the GT Selection and Configuration tab.
rxheader_out_* Input RXUSRCLK2

RX header signal from GT to core.

This port is available when the Include GT subcore in the example design option is selected in the GT Selection and Configuration tab.
rxheadervalid_out_* Input RXUSRCLK2

RX header valid signal from GT to core.

This port is available when the Include GT subcore in the example design option is selected in the GT Selection and Configuration tab.
tx_serdes_data_in_* Output TXUSRCLK2

TX data signal from core to GT.

This port is available when the Include GT subcore in example design option is selected in the GT Selection and Configuration tab.
txheader_in_* Output TXUSRCLK2

TX header signal from core to GT.

This port is available when the Include GT subcore in the example design option is selected in the GT Selection and Configuration tab.
gtwiz_reset_clk_freerun_in_0 Input  

Free running input clock to core.

Versal devices only. This port is available when the Control and Statistics interface is selected from the Configuration tab.
gtwiz_reset_all_in_0 Input  

sys_reset signal from the user.

Versal devices only. This port is available when the Control and Statistics interface is selected from the Configuration tab.
gtpowergood_in_0 Input   Refer to the UltraScale Architecture GTH Transceivers User Guide (UG576) or the UltraScale Architecture GTY Transceivers User Guide (UG578) for the port description.
tx_pma_resetdone_0 Input   TX PMA resetdone signal from GT to Core indicates lane0 status. (Versal devices only).
rx_pma_resetdone_0 Input   RX PMA resetdone signal from GT to Core indicates lane0 status. (Versal devices only).
mst_tx_resetdone_0 Input   TX master resetdone signal from GT to Core indicates lane0 status. (Versal devices only).
mst_rx_resetdone_0 Input   RX master resetdone signal from GT to Core indicates lane0 status. (Versal devices only).
rx_resetdone_in_0 Output   RX user ready output signal from Core to example design. (Versal devices only).
tx_resetdone_in_0 Output   TX user ready output signal from Core to example design. (Versal devices only).
mst_tx_reset_0 Output   TX master reset output signal from Core to GT of Lane0. (Versal devices only).
mst_tx_dp_reset_0 Output   TX reset output signal from gt reset ip to the core (Versal devices only).
mst_rx_reset_0 Output   RX master reset output signal from Core to GT of Lane0. (Versal devices only).
mst_rx_dp_reset_0 Output   RX reset output signal from gt reset ip to the core (Versal devices only).
txuserrdy_out_0 Output   TX user ready output signal from Core (reset Interface IP) to GT of Lane0. (Versal devices only).
rxuserrdy_out_0 Output   RX user ready output signal from Core (reset Interface IP) to GT of Lane0. (Versal devices only).