User Interface - 1.2 English

USXGMII Ethernet Subsystem Product Guide (PG251)

Document ID
PG251
Release Date
2023-12-12
Version
1.2 English

General purpose I/Os (GPIOs) are provided to control the example design. The user input and user output ports are described in the following table.

Table 1. User Input and User Output Ports
Name Direction Description
sys_reset Input Reset for USXGMII core
gt_ref_clk_p Input Differential input clk to GT.
gt_ref_clk_n Input Differential input clk to GT.
dclk Input Stable/free running input clk to GT.
rx_gt_locked_led_0 Output Indicates that GT has been locked.
rx_block_lock_led_0 Output Indicates RX block lock has been achieved.
restart_tx_rx_0 Input This signal is used to restart the packet generation and reception or the data sanity test when the packet generator and the packet monitor are in idle state.
completion_status Output

This signal represents the test status/result.

5’d0 Test did not run.

5’d1 - PASSED 25GE/10GE CORE TEST SUCCESSFULLY COMPLETED

5'd2 - No block lock on any lanes.

5'd3 - Not all lanes achieved block lock.

5'd4 - Some lanes lost block lock after achieving block lock.

5'd5 - No lane sync on any lanes.

5'd6 - Not all lanes achieved sync.

5'd7 - Some lanes lost sync after achieving sync.

5'd8 - No alignment status or rx_status was achieved.

5'd9 - Loss of alignment status or rx_status after both were achieved.

5'd10 - TX timed out.

5'd11 - No TX data was sent.

5'd12 - Number of packets received did not equal the number of packets sent.

5'd13 - Total number of bytes received did not equal the total number of bytes sent.

5'd14 - A protocol error was detected.

5'd15 - Bit errors were detected in the received packets.

5'd31 - Test is stuck in reset.