The following table shows the relationship between the AMD Vivado™ IDE and the user parameters (which can be viewed in the Tcl Console).
| Vivado IDE Parameter/Value 1 | User Parameter/Value 1 | Default Value |
|---|---|---|
|
CORE USXGMII MAC+PCS/PMA 32-bit |
CORE USXGMII MAC+PCS/PMA 32-bit |
USXGMII MAC+PCS/PMA 32-bit |
|
NUM_OF_CORES 1 2 3 4 |
NUM_OF_CORES 1 2 3 4 |
1 |
|
CLOCKING Asynchronous |
CLOCKING Asynchronous |
“Asynchronous” |
|
DATA_PATH_INTERFACE AXI4-Stream |
DATA_PATH_INTERFACE AXI4-Stream |
“AXI4-Stream” |
|
INCLUDE_AUTO_NEG_LOGIC True |
INCLUDE_AUTO_NEG_LOGIC 1 |
1 |
|
INCLUDE_AXI4_INTERFACE Control and Status Vectors Include AXI4-Lite |
INCLUDE_AXI4_INTERFACE 0 1 |
0 |
|
INCLUDE_STATISTICS_COUNTER True False |
INCLUDE_STATISTICS_COUNTER 0 1 |
1 |
|
ENABLE_FLOW_CONTROL_LOGIC True False |
ENABLE_FLOW_CONTROL_LOGIC 0 1 |
0 |
|
ENABLE_TIME_STAMPING True False |
ENABLE_TIME_STAMPING 0 1 |
0 |
|
PTP_OPERATION_MODE Two Step |
PTP_OPERATION_MODE 2 |
2 |
|
PTP_CLOCKING_MODE Ordinary Clock Transparent Clock |
PTP_CLOCKING_MODE 0 1 |
0 |
|
TX_LATENCY_ADJUST TRUE FALSE |
TX_LATENCY_ADJUST 1 0 |
0 |
|
ENABLE_VLANE_ADJUST_MODE TRUE FALSE |
ENABLE_VLANE_ADJUST_MODE 1 0 |
0 |
|
GT_LOCATION Include GT subcore in core Include GT subcore in example design |
GT_LOCATION 1 0 |
1 |
|
GT_REF_CLK_FREQ 161.1328125 195.3125 201.4160156 257.8125 322.265625 |
GT_REF_CLK_FREQ 161.1328125 195.3125 201.4160156 257.8125 322.265625 |
161.1328125 |
|
GT_DRP_CLK 10 to 250 |
GT_DRP_CLK 10 to 250 |
100 |
|
GT_TYPE GTY GTH |
GT_TYPE GTY GTH |
GTY |
|
GT_GROUP_SELECT (options based of device/package) |
GT_GROUP_SELECT (options based of device/package) |
X0Y0 |
|
LANE1_GT_LOC X0Y0 X0Y1 X0Y2 X0Y3 |
LANE1_GT_LOC X0Y0 X0Y1 X0Y2 X0Y3 |
|
|
LANE2_GT_LOC X0Y1 X0Y2 X0Y3 |
LANE2_GT_LOC X0Y1 X0Y2 X0Y3 |
|
|
LANE3_GT_LOC X0Y2 X0Y3 |
LANE3_GT_LOC X0Y2 X0Y3 |
|
|
LANE4_GT_LOC X0Y3 |
LANE4_GT_LOC X0Y3 |
|
|
ENABLE_PIPELINE_REG TRUE FALSE |
ENABLE_PIPELINE_REG 1 0 |
0 |
|
ADD_GT_CNTRL_STS_PORTS TRUE FALSE |
ADD_GT_CNTRL_STS_PORTS 1 0 |
0 |
|
INCLUDE_SHARED_LOGIC Include Shared Logic in core Include Shared Logic in example design |
INCLUDE_SHARED_LOGIC 1 0 |
1 |
|
FAST_SIM_MODE TRUE FALSE |
FAST_SIM_MODE 1 0 |
0 |
|
||