The Video Codec Unit (VCU) core supports one clocking topology, the internal phase locked loop (PLL). An internal VCU PLL drives the high frequency core (667 MHz) and MCU (444 MHz) clocks based on an input reference clock from the programmable logic (PL). The internal PLL generates a clock for the encoder and decoder blocks.
Note: All AXI clocks are supplied with clocks from external PL sources. These clocks are asynchronous to core encoder and decoder block clocks. The encoder and decoder blocks handle asynchronous clocking in the AXI ports.
The VCU core is reset under the following conditions:
- Initially while the PL is in power-up/configuration mode, the VCU core is held in reset.
- After the PL is fully configured, a PL based reset signal can be used to reset the VCU for initialization and bring-up. Platform management unit (PMU) in the processing system (PS) can drive this reset signal to control the reset state of the VCU.
- During partial reconfiguration (PR), the VCU block is kept under reset if it is part of the dynamically reconfigurable module.