Connectivity with VCU DDR4 Controller IP - 2023.1 English

H.264/H.265 Video Codec Unit v1.2 Solutions LogiCORE IP Product Guide (PG252)

Document ID
PG252
Release Date
2023-05-16
Version
2023.1 English
Figure 1. Connecting to the VCU IP

Table 1. AXI Ports Map and Priority
AXI Ports Mapping Port Priority
S_AXI_PORT_0 M_AXI_DEC_0 (VCU) HIGH
S_AXI_PORT_1 M_AXI_DEC_1 (VCU) HIGH
S_AXI_PORT_2 M_AXI_MCU (VCU) LOW
S_AXI_PORT_3 Zynq processor LOW
S_AXI_PORT_4 Zynq processor HIGH

Port Priority Rationale

To achieve the best port performance and memory bandwidth usage, the following priority is provided and also hardcoded in the drop.

The ports consuming the highest bandwidth using the decoder ports and Zynq UltraScale+ MPSoC frame fetch are provided the highest priority. The other two ports that consume lower bandwidth are provided the lowest priority in the arbitration. This configuration is tested to provide the best performance.

Refer to the UltraScale Architecture-Based FPGAs Memory IP LogiCORE IP Product Guide (PG150) for information regarding PCB Guidelines for DDR4, Pin and Bank Rules, Protocol Description, Performance, DIMM Configurations, Setting Timing Options, and M and D Support for Reference Input Clock Speed.