The Video Codec Unit (VCU) core is a dedicated hardware block in the
programming logic (PL). All interfaces are connected through AXI interconnect blocks in
the PL. The VCU core is AXI4 compliant on its AXI master interfaces.
It can be connected to the
ports of the PS or AXI compliant interface of the PL memory controller. There are no
direct (hardwired) connections from the VCU to the processing system (PS). HP0 to HP4
AXI ports are recommended for PS-DDR video application.
For high bandwidth VCU applications requiring simultaneous encoder and decoder operation, the encoder should be connected to the PS DDR and the decoder should be connected to the PL DDR. Refer to Zynq UltraScale+ EV Architecture Video Codec Unit DDR4 LogiCORE IP v1.1 for more information. This approach makes most effective use of limited AXI4 read/write issuance capability in minimizing latency for the decoder. DMA buffer sharing requirements will determine how capture, display, and intermediate processing stages should be mapped to PS or PL DDR.
The register programming interface of the VCU core connects to PS General Purpose (GP) ports. The clock can be used from PL or through an internal PLL inside the VCU core.