As illustrated in the following figure, glass-to-glass latency (L) is the sum of the following:
- Camera latency
- On-chip latency (L1)
- Source frame buffer DMA latency
- Encoder latency
- Transmission bitstream buffer latency
- Network or storage latency
- On-chip latency (L2)
- Coding Picture Buffer (CPB)/jitter buffer latency
- Decoder latency
- Decoded picture buffer (DPB) latency
- Display frame buffer DMA latency
- Display monitor latency
When B-frames are enabled, one frame of latency is incurred for each B-frame due to the usage of the reordering buffer. To optimize the CPB latency, a handshaking mechanism in PL is required between decoder and the display DMA. It is assumed that both capture side and display side works on a common VSYNC timing.
VSYNC timing can be asynchronous and a clock recovery mechanism is needed to synchronize source timing with sync.
With independent VSYNC timing and without clock recovery mechanism, it requires one additional frame latency to synchronize with the display devices.
Figure 1. Glass to Glass Latency
Note: These numbers do not include the latency information from the interconnect in the fabric. For more information on memory parts, see the UltraScale Architecture-Based FPGAs Memory IP LogiCORE IP Product Guide (PG150).