Interfacing the Core with Zynq UltraScale+ MPSoC Devices - 2023.1 English

H.264/H.265 Video Codec Unit v1.2 Solutions LogiCORE IP Product Guide (PG252)

Document ID
PG252
Release Date
2023-05-16
Version
2023.1 English

To integrate the VCU core into an IP integrator (IPI) block design, follow these steps:

  1. Launch the Vivado IDE and create a new project.

  2. Click Next on New Project wizard until you reach the Family Selection window.
  3. Select a target device for the VCU core.

  4. Click on the Project Settings window. Click Implementation.

  5. In the Settings window, enable the Performance Explore option by selecting Settings > Implementation > Options > Strategy: Performance_Explore See the Vivado Design Suite User Guide: Design Analysis and Closure Techniques (UG906) for more information.
  6. Click Create Block Design.
  7. Click Add IP and type VCU. The following IP appears.

  8. Add Zynq UltraScale+ VCU to the block design.
  9. Add Zynq UltraScale+ MPSoC IP to the block design as shown.

  10. Configure Zynq UltraScale+ MPSoC to enable AXI slave interfaces, clocking, and PL-PS interrupt signal per your design requirements. Refer to the Zynq UltraScale+ MPSoC Processing System LogiCORE IP Product Guide (PG201) for configuration options of the Zynq UltraScale+ MPSoC IP.

    The following figure shows an example of configuring the PS-PL interface signals.

  11. Select PL1 clock frequency as 300 MHz.

  12. Enable IRQ0 [0-7] and enable the following master, slave interfaces as shown in figure below. Also set the data width of S_AXI_HPC0_FPD to 32 bits.

  13. Connect the following interfaces manually:
    • Zynq UltraScale+ VCU.M_AXI_ENC0 to Zynq UltraScale+ MPSoC.S_AXI_HP0_FPD
    • Zynq UltraScale+ VCU.M_AXI_ENC10 to Zynq UltraScale+ MPSoC.S_AXI_HP1_FPD
    • Zynq UltraScale+ VCU.M_AXI_DEC0 to Zynq UltraScale+ MPSoC.S_AXI_HP2_FPD
    • Zynq UltraScale+ VCU.M_AXI_DEC1 to Zynq UltraScale+ MPSoC.S_AXI_HP3_FPD
    • Zynq UltraScale+ VCU.M_AXI_MCU to Zynq UltraScale+ MPSoC.S_AXI_HPC0_FPD

    Note the selection of MPSoC.S_AXI_HP1_FPD, MPSoC.S_AXI_HP0_FPD, and MPSoC.S_AXI_HP3_FPD. These are non-coherent, high-performance DMA ports for large datasets. They support AXI FIFO QoS-400 traffic shaping. For each of these ports, there is an associated register set. The register addresses are needed for command line configuration of quality of service and issuing capability using the devmem command.

    The address and description of S_AXI_HP1_FPD can be found in Zynq UltraScale+ Device Register Reference (UG1087). The address is 0xFD390000. The register is used to configure QoS and the FIFO. It is part of the AFIFM Module. The AFIFM Module documentation provides relative addresses and values for fields defining traffic priority and maximum number of read or write commands.

  14. Perform the following connections manually:
    • Instantiate a Processor System Reset and AXI Interconnect IP’s.
    • Set number of Master and Slave interfaces of AXI Interconnect to 1 each.
    • Connect M_AXI_HPM0_LPD of Zynq UltraScale+ MPSoC to S00_AXI interface of AXI Interconnect.
    • Connect M00_AXI of AXI Interconnect to S_AXI_LITE interface of VCU.
    • Connect pl_clk0 of Zynq UltraScale+ MPSoC to IP’s as described below:
      • AXI Interconnect: ACLK, S00_ACLK, M00_ACLK of AXI Interconnect.
      • VCU: s_axi_lite_aclk, m_axi_mcu_aclk
      • Zynq UltraScale+ MPSoC: saxihpc0_fpd_aclk, maxihpm0_lpd_aclk
      • Processor System Reset: slowest_sync_clk
  15. Perform the following connections manually:
    • Connect pl_resetn0 of Zynq UltraScale+ MPSoC to ext_reset_in, aux_reset_in pins of Processor System Reset.
    • Connect ‘interconnect_aresetn’ port of Processor System reset as a reset input to the S00_ARESETN, ARESETN, and M00_ARESETN ports of AXI Interconnect as shown in the following figure below. Notice the highlighted path.

    • Connect the vcu_host_interrupt port of Zynq UltraScale+ VCU to the pl_ps_irq0 port of Zynq UltraScale+ MPSoC IP.
  16. Connect the following clock ports of each IP specified below to the pl_clk1 output of Zynq UltraScale+ MPSoC core:
    • VCU: m_axi_enc_aclk
    • VCU: m_axi_dec_aclk
    • Zynq UltraScale+ MPSoC: saxihp0_fpd_aclk
    • Zynq UltraScale+ MPSoC: saxihp1_fpd_aclk
    • Zynq UltraScale+ MPSoC: saxihp2_fpd_aclk
    • Zynq UltraScale+ MPSoC: saxihp3_fpd_aclk
  17. Connect the vcu_resetn signal of Zynq UltraScale+ VCU to peripheral_aresetn pin of Processor System reset.
  18. Instantiate a Clocking Wizard IP.
  19. Set the output clock frequency to 59Mhz. Connect the clk_in1 pin of clocking wizard to pl_clk0 of Zynq UltraScale+ MPSoC. Also connect the clk_out1 pin to pll_ref_clk of VCU.
  20. In the Address Editor tab, expand EncData address segment and auto assign the addresses. The following table shows an example address map.

  21. Click on Validate Block Design to validate the connections.

  22. Create a top-level Vivado wrapper by right-clicking on Block Design and selecting Create HDL Wrapper option as shown in the following figure.

  23. Click on the Run Synthesis, Run Implementation, or Generate Bitstream option.