Port Descriptions - 2023.1 English

H.264/H.265 Video Codec Unit v1.2 Solutions LogiCORE IP Product Guide (PG252)

Document ID
PG252
Release Date
2023-05-16
Version
2023.1 English

AXI Clock Port/Reset Port Connection

The following figure shows the block diagram of the VCU Sync IP core that has seven input AXI ports and two output AXI ports.

S_AXI_CTRL_ACLK/S_AXI_MM_ALCLK/S_AXI_MM_P_ACLK
The AXI ports work with respect to this clock and reset. The clock frequency used for the Sync IP is 300 MHz.
S_AXI_CTRL_ARESETN/S_AXI_CTRL_MM_ARESETN/S_AXI_CTRL_MM_P_ARESETN
An active-Low reset is used in the Sync IP.
Figure 1. Sync IP