Resource Utilization - 2023.1 English

H.264/H.265 Video Codec Unit v1.2 Solutions LogiCORE IP Product Guide (PG252)

Document ID
PG252
Release Date
2023-05-16
Version
2023.1 English

For details about performance and resource use, see Table 1.

Table 1. Sync IP Multistream Utilization
Name PLDDR PSDDR
CLB LUTS (230400) 21587 21466
CLB Registers (460800) 30554 30356
CARRY8 (28800) 1620 1620
F7 MUXES (11520) 215 165
F8 MUXES (57600) 4 0
BLOCK RAM TILE (312) 8 8
DSPs (1728) 0 0
HPIOBDIFFINBUF (192) 0 0
BITSLICE_RX_TX (416) 0 0
GLOBAL CLOCK BUFFERS (544) 0 0
PLL (16) 0 -
MMCM (8) 0 -
Note: The Sync IP logic core GUI has an option of selecting the DDR4 memory size depending on the requirement. Table 1 gives the full address width utilization.