5G NR Control Interface Definition for LDPC Decode - 1.1 English

Soft-Decision FEC Integrated Block LogiCORE IP Product Guide (PG256)

Document ID
PG256
Release Date
2022-10-19
Version
1.1 English

When the 5G NR standard is supported the control data interface is 40 bits with the fields shown in the following table for LDPC decode.

Table 1. 5G NR Control Interface Definition for LDPC Decode
Field Bits Range Description
max_schedule 39:38 0 to 3

Maximum number of blocks that can be interleaved by the LDPC decoder while processing this block. See LDPC Block Interleaving for details.

0 = Default scheduling behavior.

mb 37:32 4 to 46 Number of parity bits as a multiple of Z (Z*mb), thereby controlling code rate
id 31:24 0 to 255 External block identifier to be passed through to status output
max_iterations 23:18 1 to 63 Maximum number of iterations
term_on_no_change 17 0 to 1

0: Do not terminate early if there is no change in hard bits for the whole block (information and parity) between iterations.

1: Terminate early if there is no change in hard bits for the whole block (information and parity) between iterations.

term_on_pass 16 0 to 1

0: Do not terminate early on passing parity check

1: Terminate early on passing parity check

include_parity_op 15 0 to 1

0: Output systematic values only

1: Output systematic values and parity

hard_op 14 0 to 1

0: Soft output

1: Hard output

  13 - Reserved
sc_idx 12:9 0 to 15 Normalization value to use on block.
bg 8:6 0 to 4 Base graph
z_set 5:3 0 to 7 Base graph cyclic shift set
z_j 2:0 0 to 7 Lifting factor (Z) j component 1
  1. The lifting factor is given by Z=a*2z_j where a is defined in Lifting Factor Component (a).