5G NR Control Interface Definition for LDPC Encode - 1.1 English

Soft-Decision FEC Integrated Block LogiCORE IP Product Guide (PG256)

Document ID
PG256
Release Date
2022-10-19
Version
1.1 English

When the 5G NR standard is supported the control data interface is 40 bits with the fields shown in the following table for LDPC encode.

Table 1. 5G NR Control Interface Definition for LDPC Encode
Field Bits Range Description
max_schedule 39:38 0 to 3

Maximum number of blocks that can be interleaved by the LDPC encoder while processing this block.

0 = Default scheduling behavior.

See LDPC Block Interleaving for details.

mb 37:32 4 to 46 Number of parity bits as a multiple of Z (Z*mb), thereby controlling code rate.
id 31:24 0 to 255 External block identifier to be passed through to status output.
  23:9 - Reserved
bg 8:6 0 to 4 Base graph
z_set 5:3 0 to 7 Base graph cyclic shift set
z_j 2:0 0 to 7 Lifting factor (Z) j component 1
  1. The lifting factor is given by Z=a*2z_j where a is defined in Lifting Factor Component (a).