5G NR Standard - 1.1 English

Soft-Decision FEC Integrated Block LogiCORE IP Product Guide (PG256)

Document ID
PG256
Release Date
2022-10-19
Version
1.1 English

When the 5G NR standard is selected in the Vivado® IDE, the SD-FEC Integrated Block is initialized with 5G NR base graphs. Code download over the AXI4-Lite interface is not required. However, the interface is still available to allow core parameters to be updated.

The code to be adopted for a particular block is provided through the CTRL interface on a block by block basis. This selection is made using four parameters: z_j, z_set, bg and mb. The bg parameter specifies the base graph 1 or 2. The lifting factor, Z, is specified using z_j and z_set, and the code rate is specified using mb. This latter parameter is the number of layers of the base matrix used, and specifies the number of parity bits mb*Z. The maximum number of information bits is 22*Z for base graph 1, and for base graph 2 is 10*Z according to the base graph selection. The rate is then:

Note that the first two Z information bits are not transmitted, so the code rate is actually as follows:

These rates do not include any padding that might be required to increase the information block size to 22*Z, or 10*Z for base graphs 1 and 2 respectively.