In 5G NR mode, the SD-FEC IP core support logic internally handles the run-time configuration of the LDPC code and shared LDPC code parameters. On receiving a particular code definition through the AXI4-Stream control interface, the support logic generates LDPC code and shared LDPC code parameters for the given LDPC code and then downloads them to the SD-FEC internal memory. In this mode, do not write LDPC code and shared LDPC code parameters using the AXI4-Lite interface because any writes makes the behavior unpredictable.
Note: For this
mode, ensure that both the CTRL (bit-0 and STATUS (bit-3) bits in the AXIS_ENABLE
register are set to 1. Writing any other value to the CTRL (bit-0) makes the behavior
unpredictable.