AXI4-Lite Interfaces - 1.1 English

Write to one of the registers, (for example, Core Parameters register AXI_WR_PROTECT) and read back a value.

Read from a register that does not have all 0s as a default to verify that the interface is functional. Output s_axi_arready asserts when the read address is valid, and output s_axi_rvalid asserts when the read data/response is valid. If the interface is unresponsive, ensure that the following conditions are met:

• The s_axi_aclk and core_clk inputs are connected and toggling.
• The core is not in reset; reset_n is active-Low.
• If the simulation has been run, verify in simulation and/or a debug feature capture that the waveform is correct for accessing the AXI4-Lite interface.