AXIS_ENABLE Register (0x10) - 1.1 English

Soft-Decision FEC Integrated Block LogiCORE IP Product Guide (PG256)
Document ID
PG256
Release Date
2022-10-19
Version
1.1 English
Table 1. AXIS_ENABLE Register
Bit Default Value Access Type Description
5 0 R/W DOUT_WORDS: Deasserts ready out and valid internally on DOUT_WORDS to disable input.
  • 0: Disabled
  • 1: Enabled
4 0 R/W DOUT: Deasserts valid out and ready internally on DOUT to disable output.
  • 0: Disabled
  • 1: Enabled
3 0 R/W STATUS 1 : Deasserts valid out and ready internally on STATUS to disable output.
  • 0: Disabled
  • 1: Enabled
2 0 R/W DIN_WORDS: Deasserts ready out and valid internally on DIN_WORDS to disable input.
  • 0: Disabled
  • 1: Enabled
1 0 R/W DIN: Deasserts ready out and valid internally on DIN to disable input.
  • 0: Disabled
  • 1: Enabled
0 0 R/W CTRL 2 : Deasserts ready out and valid internally on CTRL to disable input.
  • 0: Disabled
  • 1: Enabled
  1. For 5G mode to function properly, STATUS must be set to Enabled (if not already set by the Vivado® IDE) before the first CTRL word is applied.
  2. For 5G mode to function properly, CTRL must be set to Enabled (if not already set by the Vivado IDE) before the first CTRL word is applied.