AXIS_WIDTH Register (0x0C) - 1.1 English

Soft-Decision FEC Integrated Block LogiCORE IP Product Guide (PG256)

Document ID
PG256
Release Date
2022-10-19
Version
1.1 English
Table 1. AXIS_WIDTH Register
Bit Default Value Access Type Description
5 0 R/W

DOUT_WORDS

  • 0: The DOUT_WORDS input is block based. Only one value is input per block on DOUT_WORDS, and this specifies the number of LLRs in each 128-bit lane for a complete block (for example, a value of 16 on DOUT_WORDS indicates that all 128 bits of each lane of DOUT should be used).
  • 1: The DOUT_WORDS input is supplied for each AXI transaction on DOUT. For every AXI transaction on DOUT there must be a corresponding transaction on DOUT_WORDS. If DOUT_WIDTH is set to use multiple lanes, then DOUT_WORDS must provide a value for each 128-bit lane as given in the table in LLR Output Words (DOUT_WORDS).
4:3 0 R/W
DOUT: Width conversion applied to DOUT and DOUT_WORDS data
  • 0: 1x128b
  • 1: 2x128b
  • 2: 4x128b
  • 3: Reserved
2 0 R/W

DIN_WORDS

  • 0: The DIN_WORDS input is block based. Only one value is input per block on DIN_WORDS, and this specifies the number of LLRs in each 128-bit lane for a complete block (for example, a value of 16 on DIN_WORDS indicates that all 128 bits of each lane of DIN should be used).
  • 1: The DIN_WORDS input is supplied for each AXI transaction on DIN. For every AXI transaction on DIN there must be a corresponding transaction on DIN_WORDS. If DIN_WIDTH is set to use multiple lanes, then DIN_WORDS must provide a value for each 128-bit lane as given in the table in Data Input Control AXI4-Stream Slave (DIN_WORDS).
1:0 0 R/W
DIN: Width conversion applied to DIN and DIN_WORDS data
  • 0: 128b
  • 1: 2x128b
  • 2: 4x128b
  • 3: Reserved
  1. This register should only be changed after reset when the interfaces are disabled.