AXI_WR_PROTECT Register (0x00) - 1.1 English

Soft-Decision FEC Integrated Block LogiCORE IP Product Guide (PG256)

Document ID
PG256
Release Date
2022-10-19
Version
1.1 English
Table 1. AXI_WR_PROTECT Register
Bit Default Value Access Type Description
0 0 R/W Prevents write to all other registers.
  • 0: Write allowed
  • 1: Write protected
  1. For 5G mode to function properly, this register must be set to 0: Write allowed (if not already set by the Vivado® IDE) before the first CTRL word is applied.