Application Summary - 1.1 English

Soft-Decision FEC Integrated Block LogiCORE IP Product Guide (PG256)

Document ID
PG256
Release Date
2022-10-19
Version
1.1 English
Figure 1. Application Flow Chart

The flow chart in the previous figure shows the basic application behavior. The detail of the application varies depending on the configuration specified for the SD-FEC IP core and example design. By default the application has the NO_IO macro defined which disables interactive functionality. The macro should be removed to enable the stdin and stdout functionality.

The Vitis software platform workspace is configured to use the MicroBlaze™ ™ Debug Module or CoreSight™ Debug for stdin and stdout as the hardware design does not include a separate UART device or enable the PS UART.

When the interactive functionality is enabled all the design parameters, defined in the example design parameters table, can be updated using the UART terminal. A basic menu system is implemented where the parameters can be updated and repeated tests run.