BYPASS Register (0x3C) - 1.1 English

Soft-Decision FEC Integrated Block LogiCORE IP Product Guide (PG256)

Document ID
PG256
Release Date
2022-10-19
Version
1.1 English
Table 1. BYPASS Register
Bit Default Value Access Type Description
0 0 R/W

Perform function with given number of iterations (early termination not supported, so associated termination bits must be set to zero in CTRL input while BYPASS is set), but output is same as input (minus tail bits for turbo decode) accounting for any soft to hard conversion.

Parity pass/CRC flag is based on input values:
  • 0: Normal operation
  • 1: Output same as input
  1. This register should only be changed when the core is not active (ACTIVE is 0).