Clocking - 1.1 English

Soft-Decision FEC Integrated Block LogiCORE IP Product Guide (PG256)

Document ID
PG256
Release Date
2022-10-19
Version
1.1 English

The SD-FEC Integrated Block operates from a separate clock to the programmable logic (PL), allowing the core to run at higher frequency.

Each interface has its own clock and clock domain crossing circuits to enable transfer of data over the interface. Certain interfaces also have width conversion to allow data bandwidth to be maintained with lower interface clock frequency. See the Zynq UltraScale+ RFSoC Data Sheet: Overview (DS889) for the maximum frequency of core and interface clocks. Lower frequencies can be used.

If the throughput and latency are limited by processing within the core, rather than by input/output, then the throughput is proportional to the core clock frequency. As such, if the core clock rate is reduced over the maximum value, there is a proportional reduction in throughput and an increase in latency relative to the maximum achievable. For example, if a 650 MHz clock is used rather than a 667 MHz clock, then the throughput at 650 MHz relative to the peak at 667 MHz is 650/667=0.975 times the peak throughput. Therefore, if the peak throughput at 667 MHz is 1 Gb/s, then the throughput at 650 MHz is 0.975 Gb/s.