This section contains information about constraining the core in the Vivado® Design Suite.
Required Constraints
The Vivado IDE implementation currently does not support automatic timing-driven placement for SD-FEC instances. To achieve optimal timing results, the instances must be placed manually:
set_property LOC FE_X<x>Y<y> [get_cells */<ipinst_name>/inst/FE_I]
Device, Package, and Speed Grade Selections
The core can be implemented in Zynq UltraScale+ RFSoC devices as detailed in the Zynq UltraScale+ RFSoC Data Sheet: Overview (DS889).
Clock Frequencies
See the Zynq UltraScale+ RFSoC Data Sheet: Overview (DS889).
Clock Management
This section is not applicable for this IP core.
Clock Placement
This section is not applicable for this IP core.
Banking
This section is not applicable for this IP core.
Transceiver Placement
This section is not applicable for this IP core.
I/O Standard and Placement
This section is not applicable for this IP core.