Control Input Ports (CTRL) - 1.1 English

Soft-Decision FEC Integrated Block LogiCORE IP Product Guide (PG256)

Document ID
PG256
Release Date
2022-10-19
Version
1.1 English

The control input bus (CTRL) is an AXI4-Stream slave interface. The control input bus uses the s_axis_ctrl_aclk clock. The control input provides information specific to each block. Its definition depends on whether 5G NR standard support is selected in the Vivado® IDE.

Table 1. Control Input Ports
Port I/O
s_axis_ctrl_aclk I
s_axis_ctrl_tvalid I
s_axis_ctrl_tready O
s_axis_ctrl_tdata[32/40] 1 I
  1. 40 bits if Standard is set to 5G, otherwise 32 bits.