Data Input Control (DIN_WORDS) - 1.1 English

If the AXIS_WIDTH register setting for DIN_WORDS is 0, then the DIN_WORDS input takes one value per block, and this specifies the number of LLR values transferred in all lanes of the DIN input (there is only one value that applies to all lanes). If the AXIS_WIDTH register setting for each transfer is 1, then the number of bytes transferred per cycle on DIN is specified by DIN_WORDS. To aid integration, the TLAST input for this interface should be driven with a 1 for the last transfer of a block. This input is not used to synchronize the input, but it is checked and an interrupt is available to signal inconsistencies.

If the data input interface is configured for soft input (that is, a decode operation is being performed), then the LLR input words (DIN_WORDS) stream specifies the number of LLR values in the respective lane of input.

If DIN is configured for hard input (that is, an LDPC encode operation is being performed), then DIN_WORDS specifies the number of bytes of hard bits transferred per cycle. In both cases, data bytes in DIN lanes are always in the least significant bytes of the DIN lane, for example, if two bytes of soft or hard bits are provided in lane 0, they are in bits 7:0 and 15:8.

DIN_WORDS is internally overridden to ensure that multiple blocks do not straddle a transaction on DIN, and the final transaction is shortened, if necessary, by reducing the bytes transferred. For example, if the AXIS_WIDTH.DIN_WORDS setting is 0, such that a single value is used over the whole block, if the block is not a multiple of the DIN_WORDS value, then the last transfer is reduced to match the actual block size. Similarly, if four lanes are in use, and DIN_WORDS is 8, 4, 2, 1 on the respective lanes 0 to 3, and there are 13 words remaining, then 8 and 4 words are transferred on lanes 0 and 1, and one word on lane 2 and zero words on lane 3. As such it is possible to keep DIN_WORDS constant over a block even if the block length is not a multiple of DIN_WORDS.