Data Input (DIN) - 1.1 English

Soft-Decision FEC Integrated Block LogiCORE IP Product Guide (PG256)

Document ID
PG256
Release Date
2022-10-19
Version
1.1 English
  • The DIN data input stream consists of four 128-bit lanes. The number of lanes used depends upon the setting of the AXIS_WIDTH.DIN parameter.
  • Either bytes of soft value LLR (decode operation), or bytes of hard bits (encode operation) are transferred over DIN.
  • Blocks are transferred over one or more cycles, starting with the least significant LLRs or hard bits.
  • The number of bytes (LLRs or hard bits) transferred over DIN on each cycle is given by the DIN_WORDS input. See Data Input Control AXI4-Stream Slave (DIN_WORDS) for details on how DIN_WORDS is used.

    For example, if a symbol demapper is generating a number of LLR values associated with a particular level of modulation, it is possible to adjust the input to accommodate this. By ensuring that each lane is controlled similarly, it allows parallel symbol demappers to be accommodated by each lane.

  • Data words are transferred in the least significant bytes of each DIN lane. For example, if DIN_WORDS specifies that two bytes are transferred in lane 0, then these bytes are llr(0) and llr(1) (bits 7:0 and 15:8).
  • Each transfer can only contain one block; a block must complete before the next can start. This might require the final transfer of a block to have one or more of the higher lane sizes set to 0 or one of the lane values to be reduced. The core enforces this internally, overriding the DIN_WORDS input to ensure that the block completes, so that the next block input can start on lane 0 of the next AXI4-Stream transaction.