Decoder Example - 1.1 English

Soft-Decision FEC Integrated Block LogiCORE IP Product Guide (PG256)

Document ID
PG256
Release Date
2022-10-19
Version
1.1 English
my_code1:
 n: 128
 k: 104
 p: 8
 scale: [11,11,11]
 sm_array:
 - {row: 0, col: 0, shift: [1,6]} # defines multiple rotations (for W>1 codes) 
 - {row: 0, col: 2, shift: 5}
 - {row: 0, col: 6, shift: 4}
 - {row: 0, col: 7, shift: 3}
 - {row: 0, col: 11, shift: 2}
 - {row: 0, col: 12, shift: 1}
 - {row: 0, col: 14, shift: 0}
 - {row: 0, col: 15, shift: 7}
 - {row: 1, col: 0, shift: 6}
 - {row: 1, col: 1, shift: 7}
 - {row: 1, col: 5, shift: 0}
 - {row: 1, col: 7, shift: 1}
 - {row: 1, col: 9, shift: 2}
 - {row: 1, col: 11, shift: 3}
 - {row: 1, col: 15, shift: 4}
 - {row: 2, col: 0, shift: 0}
 - {row: 2, col: 3, shift: 1}
 - {row: 2, col: 4, shift: 2}
 - {row: 2, col: 8, shift: 3}
 - {row: 2, col: 9, shift: 4}
 - {row: 2, col: 10, shift: 5}
 - {row: 2, col: 13, shift: 6}