29 |
0 |
WO |
LDPC REF NM_NMQC Table ECC two-bit error (5G NR mode)/ LDPC
CODE REG ECC two-bit error (Initialized non-5G mode)
2,
3
|
28 |
0 |
WO |
LDPC REF QC Table ECC two-bit error
2,
3
|
27 |
0 |
WO |
LDPC REF LA Table ECC two-bit error
2,
3
|
26 |
0 |
WO |
LDPC REF SC Table ECC two-bit error
2,
3
|
25 |
0 |
WO |
LDPC REF NM_NMQC Table ECC event (5G NR mode)/ LDPC CODE REG
ECC event (Initialized non-5G mode)
2,
4
|
24 |
0 |
WO |
LDPC REF QC Table ECC event
2
|
23 |
0 |
WO |
LDPC REF LA Table ECC event
2
|
22 |
0 |
WO |
LDPC REF SC Table ECC event
2
|
21 |
0 |
WO |
LDPC final parity calc memory ECC two-bit error
3
|
20 |
0 |
WO |
LDPC QC_TABLE memory 3 ECC two-bit error
3
|
19 |
0 |
WO |
LDPC QC_TABLE memory 2 ECC two-bit error
3
|
18 |
0 |
WO |
LDPC QC_TABLE memory 1 ECC two-bit error
3
|
17 |
0 |
WO |
LDPC QC_TABLE memory 0 ECC two-bit error
3
|
16 |
0 |
WO |
LDPC LA_TABLE memory ECC two-bit error
3
|
15 |
0 |
WO |
LDPC SC_TABLE memory ECC two-bit error
3
|
14 |
0 |
WO |
LDPC code REG3 memory ECC two-bit error
3
|
13 |
0 |
WO |
LDPC code REG2 memory ECC two-bit error
3
|
12 |
0 |
WO |
LDPC code REG1 memory ECC two-bit error
3
|
11 |
0 |
WO |
LDPC code REG0 memory ECC two-bit error
3
|
10 |
0 |
WO |
LDPC final parity calc memory ECC event
4
|
9 |
0 |
WO |
LDPC QC_TABLE memory 3 ECC event |
8 |
0 |
WO |
LDPC QC_TABLE memory 2 ECC event |
7 |
0 |
WO |
LDPC QC_TABLE memory 1 ECC event |
6 |
0 |
WO |
LDPC QC_TABLE memory 0 ECC event |
5 |
0 |
WO |
LDPC LA_TABLE memory ECC event |
4 |
0 |
WO |
LDPC SC_TABLE memory ECC event |
3 |
0 |
WO |
LDPC code REG3 memory ECC event |
2 |
0 |
WO |
LDPC code REG2 memory ECC event |
1 |
0 |
WO |
LDPC code REG1 memory ECC event |
0 |
0 |
WO |
LDPC code REG0 memory ECC event |
- Read 0. Write 1 to respective bit to disable
interrupt (respective bit of ECC Interrupt Mask register is set to 1). Write 0
ignored.
- These memories exist
in the SD-FEC support logic in 5G NR and initialized non-5G modes.
- The ECC two-bit error register is set when
two errors are detected in a word read from the respective memory. It can also
be set when the number of errors in a word is greater than two—however, this is
not guaranteed. Uncorrected multi-bit errors can result in incorrect core
behavior. A core reset is recommended, followed by re-programming of the LDPC
code parameters.
- An ECC event is when one or more errors have
been detected in a word read from the respective memory. If present without an
ECC two-bit error then only a single error has been detected, which has been
corrected. To avoid this potentially becoming an uncorrectable two-bit error at
a later time the memory contents should be refreshed.
|