ECC Interrupt Status Register (0x2C) - 1.1 English

Soft-Decision FEC Integrated Block LogiCORE IP Product Guide (PG256)
Document ID
PG256
Release Date
2022-10-19
Version
1.1 English
Table 1. ECC Interrupt Status Register
Bit 1 Default Value Access Type Description 2
29 0 R/W LDPC REF NM_NMQC Table ECC two-bit error (5G NR mode)/ LDPC CODE REG ECC two-bit error (Initialized non-5G mode) 3, 4
28 0 R/W LDPC REF QC Table ECC two-bit error 3, 4
27 0 R/W LDPC REF LA Table ECC two-bit error 3, 4
26 0 R/W LDPC REF SC Table ECC two-bit error 3, 4
25 0 R/W LDPC REF NM_NMQC Table ECC event (5G NR mode)/ LDPC CODE REG ECC event (Initialized non-5G mode) 3, 5
24 0 R/W LDPC REF QC Table ECC event 3
23 0 R/W LDPC REF LA Table ECC event 3
22 0 R/W LDPC REF SC Table ECC event 3
21 0 R/W LDPC final parity calc memory ECC two-bit error 4
20 0 R/W LDPC QC_TABLE memory 3 ECC two-bit error 4
19 0 R/W LDPC QC_TABLE memory 2 ECC two-bit error 4
18 0 R/W LDPC QC_TABLE memory 1 ECC two-bit error 4
17 0 R/W LDPC QC_TABLE memory 0 ECC two-bit error 4
16 0 R/W LDPC LA_TABLE memory ECC two-bit error 4
15 0 R/W LDPC SC_TABLE memory ECC two-bit error 4
14 0 R/W LDPC code REG3 memory ECC two-bit error 4
13 0 R/W LDPC code REG2 memory ECC two-bit error 4
12 0 R/W LDPC code REG1 memory ECC two-bit error 4
11 0 R/W LDPC code REG0 memory ECC two-bit error 4
10 0 R/W LDPC final parity calc memory ECC event 5
9 0 R/W LDPC QC_TABLE memory 3 ECC event
8 0 R/W LDPC QC_TABLE memory 2 ECC event
7 0 R/W LDPC QC_TABLE memory 1 ECC event
6 0 R/W LDPC QC_TABLE memory 0 ECC event
5 0 R/W LDPC LA_TABLE memory ECC event
4 0 R/W LDPC SC_TABLE memory ECC event
3 0 R/W LDPC code REG3 memory ECC event
2 0 R/W LDPC code REG2 memory ECC event
1 0 R/W LDPC code REG1 memory ECC event
0 0 R/W LDPC code REG0 memory ECC event
  1. Write 1 to respective bit to clear.
  2. This register reflects the raw interrupt status and is not masked by the IMR.
  3. These memories exist in the SD-FEC support logic in 5G NR and initialized non-5G modes.
  4. The ECC two-bit error register is set when two errors are detected in a word read from the respective memory. It can also be set when the number of errors in a word is greater than two—however, this is not guaranteed. Uncorrected multi-bit errors can result in incorrect core behavior.
  5. An ECC event is when one or more errors have been detected in a word read from the respective memory. If present without an ECC two-bit error then only a single error has been detected, which has been corrected.