There are two example designs available. By default, the SD-FEC core generates a simulation-only example design, containing the IP instance and an example test bench. The default example design should not be used for synthesis/implementation as it contains only the IP instance. An optional processor (PS)-based example design can be selected during IP customization; see Example Design Tab for more information. The PS example design can be used to generate a bitstream. When generated, to open the example design, right-click on the IP instance in the project manager and select Open Example Design.