Example Design Statistics - 1.1 English

Soft-Decision FEC Integrated Block LogiCORE IP Product Guide (PG256)

Document ID
PG256
Release Date
2022-10-19
Version
1.1 English

The statistics in the following table are captured by the design.

Table 1. Example Design Statistics
Statistics Description
Statistics block
raw_berr Channel bit error count
raw_blerr Channel block error count
cor_berr Uncorrected bit error count after decode
cor_blerr Uncorrected block error count after decode
iter_cnt Decode iteration count
Monitor Blocks 1
first Time stamp (counter value) of the last transaction (tlast = 1) of the first code block run through the system
last Time stamp (counter value) of the last transaction (tlast = 1) of the last code block run through the system
stalled The number of system clock cycles when the downstream IP has deasserted tready causing the upstream IP to be throttled, that is, tvalid is High and tready is Low.
  1. Duplicated for each instance; encoder I/P, encoder O/P, decoder I/P, and decoder O/P.