This tab is used to set the example design parameters.
The core always generates the default simulation-only example test bench example design. A processor-based example design can also be selected; this is included in the example design along with the default example test bench.
- Generate processor-based example design
- Select the generation of the processor based example design in the example design project.
- Processor-based example design type
- Select
MicroBlaze™
or
Zynq®
UltraScale+™ RFSoC.
- Selecting MicroBlaze enables simulation of the full processor-based example design.
- Selecting Zynq UltraScale+ RFSoC creates an example design using the Processor Sub-System (PS).
Example design generation also builds an example processor application.
- Include Encoder instance
- When selected the generated example design also includes an instance of the LDPC Encoder/Decoder IP core configured for encode. This option is only available when LDPC Encode or Decode has been selected and the core is able to determine a LDPC code definition compatible with the LDPC encoder.
- Build Vitis Project
- Optionally attempt to create and build the example processor application during example design generation. This step requires the Xilinx® Software Command-Line Tool (XSCT) to be available. The generated ELF is imported into the example design and associated with the MicroBlaze processor, enabling simulation of the example design.