Example Soft Value Mapping for LDPC Decode Input - 1.1 English

Soft-Decision FEC Integrated Block LogiCORE IP Product Guide (PG256)

Document ID
PG256
Release Date
2022-10-19
Version
1.1 English

The following table provides an example for the case of LDPC decoder of how a 5-bit integer range of input is mapped to the soft value (that is, no fractional bits). Note that inputs that are out of range have been saturated (symmetrically).

Table 1. Example Soft Value Mapping for LDPC Decode Input
Original Value Original 5-bit Twos Complement Integer Representation DIN Value DIN input Comment
+15.0 01111 +7.75 00011111 Sign extended and saturated
…...
+8.0 01000 +7.75 00011111 Sign extended and saturated
+7.0 00111 +7.0 00011100 Sign extended
+6.0 00110 +6.0 00011000 Sign extended
...…
0.0 00000 0.0 00000000 Sign extended
…...
-6.0 11010 -6.0 11101000 Sign extended
-7.0 11001 -7.0 11100100 Sign extended
-8.0 11000 -7.75 11100001 Sign extended and saturated (symmetrically)
...…
-15.0 10001 -7.75 11100001 Sign extended and saturated (symmetrically)

Note that values in the previous table assume a direct mapping without scaling. Better performance might be achieved by scaling the input by a value less than 1 to reduce or completely avoid saturation. System simulations should be performed to determine the best use of input range for a particular code, channel and symbol mapping. Also, adjustment of the normalization factor might improve performance (where 0.75 is a good starting point).

When LLR input is for turbo decode, then LLRs for Systematic, Parity and Parity Interleaved are provided interleaved for the K inputs, followed by 12 tail bits as shown in the following table.

Table 2. Turbo Decode LLR Tail Bits
Item Value
0 Systematic LLR (0)
1 Parity LLR (0)
2 Parity Interleaved LLR (0)
...… ...…
3K-3 Systematic LLR (K-1)
3K-2 Parity LLR (K-1)
3K-1 Parity Interleaved LLR (K-1)
3K Systematic (K)
3K+1 Parity LLR LLR (K)
3K+2 Systematic LLR (K+1)
3K+3 Parity LLR (K+1)
3K+4 Systematic LLR (K+2)
3K+5 Parity LLR (K+2)
3K+6 Systematic Interleaved LLR (K)
3K+7 Parity Interleaved LLR (K)
3K+8 Systematic Interleaved LLR (K+1)
3K+9 Parity Interleaved LLR (K+1)
3K+10 Systematic Interleaved LLR (K+2)
3K+11 Parity Interleaved LLR (K+2)