Features - 1.1 English

The SD-FEC core is a highly flexible soft-decision FEC decoder and LDPC encoder offering the following features:

• Function configurable between either:
  • LDPC decode or encode of customer-specified Quasi-cyclic (QC) codes, including standard and custom, or
  • Turbo decode of codes used by LTE
• Peak throughput of the order:
  • 1.78 Gb/s turbo decode @ 6 iterations
  • 2.84 Gb/s for LDPC decode @ 8 iterations
  • 19.82 Gb/s for LDPC encode
• Scalable implementation
  • Multiple instantiations on a device (see Placement Location Guidelines for SD-FEC IP Core)
• High bandwidth AXI4-Stream interfaces