By default, the SD-FEC core generates a simulation-only example design, containing the IP instance and an example test bench. The default example design should not be used for synthesis/implementation because it contains only the core instance.
- Ensure that all the timing constraints for the core were properly incorporated from the example design and that all constraints were met during implementation.
- Does it work in post-place and route timing simulation? If problems are seen in hardware but not in timing simulation, this could indicate a PCB issue. Ensure that all clock sources are active and clean.
- If using MMCMs in the design, ensure that all MMCMs have obtained lock by
monitoring the
lockedport.
The core supports a BYPASS capability. This performs the same operation (so takes the same number of cycles, but without changing data between input and output).