| Signal | I/O | Clock Domain | Description |
|---|---|---|---|
| reset_n | I | None | Master asynchronous reset |
| core_clk | I | core_clk | Main processing clock for processing core |
| interrupt 1 | O | s_axi_aclk | Indicates error conditions. Behavior controlled by interrupt control registers. |
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| Signal | I/O | Clock Domain | Description |
|---|---|---|---|
| reset_n | I | None | Master asynchronous reset |
| core_clk | I | core_clk | Main processing clock for processing core |
| interrupt 1 | O | s_axi_aclk | Indicates error conditions. Behavior controlled by interrupt control registers. |
|
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