Hard Input for LDPC Encode - 1.1 English

Soft-Decision FEC Integrated Block LogiCORE IP Product Guide (PG256)

Document ID
PG256
Release Date
2022-10-19
Version
1.1 English

When encoding, only hard data is input. This is provided in bytes, with up to 64 bytes transferred per cycle depending on the setting of the AXIS_WIDTH.DIN parameter.

Table 1. LLR Input AXI4-Stream Slave (DIN) Interface Definition for Hard Bits
Bit Width for Each AXIS_WIDTH.DIN Setting Field Bits Description
4x 2x 1x
512b 256b 128b hbyte(0) 7:0 Bits m(7:0) to be encoded
...…    
hbyte(15) 127:120 Bits m(127:120) to be encoded
Unused hbyte(31:16) 255:128 Bits m(255:128) to be encoded
Unused hbyte(63:32) 511:256 Bits m(511:256) to be encoded

Only the information bits (which consists of K bits) must be provided. To aid integration, the TLAST input for this interface should be driven with a 1 for the last transfer of a block. This input is not used for synchronization of the input, but it is checked and an interrupt is available to signal inconsistencies.