Hard Output for LDPC and Turbo Decode and LDPC Encode - 1.1 English

Soft-Decision FEC Integrated Block LogiCORE IP Product Guide (PG256)

Document ID
PG256
Release Date
2022-10-19
Version
1.1 English

When the hard_op bit is 1 then only hard bits are output. This is provided in bytes, with up to 64 bytes transferred per cycle dependent on the setting of AXIS_WIDTH.DOUT parameter as summarized in the following table.

Table 1. LLR Output AXI4-Stream Slave (DOUT) Interface Definition Configured for Hard Bits
Bit Width for Each AXIS_WIDTH.DOUT Setting Field Bits Description
4x 2x 1x
512b 256b 128b hbyte(0) 7:0 Bits m(7:0)
…...    
hbyte(15) 127:120 Bits m(127:120)
Unused hbyte(31:16) 255:128 Bits m(255:128)
Unused hbyte(63:32) 511:256 Bits m(511:256)