LogiCORE IP Facts Table | |
---|---|
Core Specifics | |
Supported Device Family 1 | Zynq® UltraScale+™ RFSoC |
Supported User Interfaces | AXI4-Lite, AXI4-Stream |
Resources | Performance and Resource Utilization web page |
Provided with Core | |
Design Files | Encrypted RTL |
Example Design | IP integrator Block Diagram |
Test Bench | Verilog |
Constraints File | Xilinx® Design Constraints (XDC) |
Simulation Model |
System Verilog SecureIP model C numerical model |
Supported S/W Driver 2 |
Standalone Linux |
Tested Design Flows 3 | |
Design Entry | Vivado® Design Suite |
Simulation | For supported simulators, see the Xilinx Design Tools: Release Notes Guide |
Synthesis | Vivado |
Support | |
Release Notes and Known Issues | Master Answer Record: 70720 |
All Vivado IP Change Logs | Master Vivado IP Change Logs: 72775 |
Xilinx Support web page | |
|