All interfaces on the SD-FEC Integrated Block have
clock-domain-crossing (CDC) FIFOs. The FIFO depths are given in the following
table.
While the inner core enforces the
DIN
/DOUT_WORDS
dependencies, the FIFOs can fill
such that a number of transfers up to the FIFO depth can occur into DIN
before being blocked by a lack of transfers on DIN_WORDS
. In
particular, this should be noted if interfaces are being disabled for some reason, the
data in the FIFOs is still processed.
Channel | FIFO Depth (For Given Interface Width Setting) | ||
---|---|---|---|
1 Lane | 2 Lanes | 4 Lanes | |
DIN, DIN_WORDS, DOUT, DOUT_WORDS | 25 transfers | 13 transfers | 7 transfers |
CTRL, STATUS | 13 transfers in 5G mode, 6 transfers otherwise |