A single interrupt output signal indicates a number of error conditions. These conditions are
defined by the Interrupt and ECC Interrupt Registers. Error conditions include:
-
tlastmissing on master interfaces: This is where atlastinput is not asserted on the last transfer relating to a block. -
tlastunexpected: This is when atlastinput is asserted unexpectedly (on all but the last transfer in a block).These conditions are described further in the AXI4-Stream Interface section. If these errors occur, then the SD-FEC core and connected circuits must be reset to resynchronize block transfer. A reset of the SD-FEC core causes the core parameter registers to be reset (which includes disabling of the interfaces) and these registers have to be reloaded (incurring a small number of cycles).
- Errors detected in ECC protected memory when a word is read through the AXI4-Lite interface, or by the LDPC decoder, when the latter is active. Both correctable single bit errors and uncorrectable two-bit errors are flagged (the latter might also include situations where there are more than two errors, but only detection of two-bit errors is guaranteed).