Interrupt Enable Register (IER) (0x20) - 1.1 English

Soft-Decision FEC Integrated Block LogiCORE IP Product Guide (PG256)
Document ID
PG256
Release Date
2022-10-19
Version
1.1 English
Table 1. Interrupt Enable Register
Bit 1 Default Value Access Type Description
5 0 WO DOUT_WORDS tlast unexpected
4 0 WO DOUT_WORDS tlast missing
3 0 WO DIN_WORDS tlast unexpected
2 0 WO DIN_WORDS tlast missing
1 0 WO DIN tlast unexpected
0 0 WO DIN tlast missing
  1. Read 0. Write 1 to respective bit to enable interrupt (respective bit of IMR is set to 0). Write 0 ignored.