Interrupt Mask Register (IMR) (0x28) - 1.1 English

Soft-Decision FEC Integrated Block LogiCORE IP Product Guide (PG256)
Document ID
PG256
Release Date
2022-10-19
Version
1.1 English
Table 1. Interrupt Mask Register
Bit Default Value Access Type Description
5 1 RO DOUT_WORDS tlast unexpected
4 1 RO DOUT_WORDS tlast missing
3 1 RO DIN_WORDS tlast unexpected
2 1 RO DIN_WORDS tlast missing
1 1 RO DIN tlast unexpected
0 1 RO DIN tlast missing
  1. If mask bit is set, then interrupt is masked, that is, it does not cause the interrupt pin to go High.