Interrupt Status Register (ISR) (0x1C) - 1.1 English

Soft-Decision FEC Integrated Block LogiCORE IP Product Guide (PG256)
Document ID
PG256
Release Date
2022-10-19
Version
1.1 English
Table 1. Interrupt Status Register
Bit 1 Default Value Access Type Description
5 0 R/W DOUT_WORDS tlast unexpected
4 0 R/W DOUT_WORDS tlast missing
3 0 R/W DIN_WORDS tlast unexpected
2 0 R/W DIN_WORDS tlast missing
1 0 R/W DIN tlast unexpected
0 0 R/W DIN tlast missing
  1. Write 1 to respective bit to clear.
  2. This register reflects the raw interrupt status and is not masked by the IMR.